1. Field of the Invention
The present invention relates to the field of output signal driving circuits. More specifically, the present invention relates to an output signal driver circuit within an input/output circuit of an integrated circuit (IC) device.
2. Background Technology
Programmable integrated circuits, such as field programmable gate arrays (FPGAs), include configurable logical blocks (CLBs), decoders, programmable input/output blocks (IOBs), and an interconnect structure for programmably interconnecting such devices. The IOBs are further coupled to the pads of the integrated circuit and receive/transmit signals over the pads. Typically, each IOB includes an input signal receiving circuit and an output signal driving circuit.
FIG. 1 illustrates a prior art output signal driver 10 located within an input/output block (IOB). Driver 10 receives an output enable signal T that tristates the output signal of buffer 18 when asserted, thereby allowing other circuitry of the IOB (e.g., an input signal receiving circuit) to input a signal over pad 20. When output enable signal T is not asserted, buffer 18 generates an output signal that is sent to pad 20. A clock enable signal CE is provided as an input signal to a multiplexer 12 and as a clock enable signal to a flip flop 14. An output signal O is also provided as an input signal to multiplexer 12. The output signal of multiplexer 12 is provided as an input signal to flip flop 14. Multiplexer 16 receives the output signal of multiplexer 12 and the output signal of flip flop 14. The output signal of multiplexer 16 is provided to the input terminal of buffer 18. Flip flop 14 is clocked by an outside or "output" clock signal OK. Note that although in the embodiments of the present invention described herein clock signal OK serves as a data signal as well as a control signal, any other signal selected by the user can be used for those functions. Multiplexers 12 and 16 have select lines that are individually coupled to programmable memory cells (e.g., SRAMs, or antifuses, or any other means for configuring logic) for configuration.
Although driver 10 is effective for many applications, the configuration memory cells (not shown) for multiplexer 12 and multiplexer 16 are set at IC initialization and not altered during the operation of the device. As such, driver 10 allows either clock enable signal CE or output signal O to be driven over pad 20. In other words, driver 10 does not allow output signal multiplexing over pad 20.
To solve this problem, in one application, a CLB adjacent to an IOB is programmed to act as a multiplexer for multiplexing of output signals over the associated pad. Note that within the periphery of a typical IC, there is typically one CLB located adjacent to two IOBs. A typical CLB contains two programmable lookup tables. Therefore, both lookup tables of a single CLB are consumed in allowing two adjacent IOBs to provide time multiplexing of output signals. This approach is not desirable because all of the CLBs adjacent to the IOBs are consumed and are not available to perform other functions. Further, since the multiplexing functions are performed by a CLB, i.e. outside of the IOB, the interconnect structure is required to link the CLB to the IOB and then out through pad 20. This configuration delays the resultant output signal.
Accordingly, a need arises for an output signal driver that allows output signal multiplexing over pad 20 without requiring a CLB. The present invention provides this feature as well as other advantages.